The disclosed technology is related to non-volatile memory.
Semiconductor memory has become increasingly popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrically Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories. With flash memory, also a type of EEPROM, the contents of the whole memory array, or of a portion of the memory, can be erased in one step, in contrast to the traditional, full-featured EEPROM.
Both traditional EEPROM and flash memory utilize a floating gate (FG) that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between the source and drain regions. A control gate (CG) is provided over and insulated from the floating gate. The threshold voltage (VTH) of the transistor thus formed is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
Some EEPROM and flash memory devices have a floating gate that is used to store two ranges of charges and, therefore, the memory element can be programmed/erased between two states, e.g., an erased state and a programmed state. Such a flash memory device is sometimes referred to as a binary flash memory device because each memory element can store one bit of data.
A multi-state (also called multi-level) flash memory device is implemented by identifying multiple distinct allowed/valid programmed threshold voltage ranges. Each distinct threshold voltage range corresponds to a predetermined value for the set of data bits encoded in the memory device. For example, each memory element can store two bits of data when the element can be placed in one of four discrete charge bands corresponding to four distinct threshold voltage ranges.
Typically, a program voltage Vpgm is applied to the control gate during a program operation as a series of pulses that increase in magnitude over time. In one possible approach, the magnitude of the pulses is increased with each successive pulse by a predetermined step size, e.g., 0.2-0.4 V. Vpgm can be applied to the control gates of flash memory elements. In the periods between the program pulses, verify operations are carried out. That is, the programming level of each element of a group of elements being programmed in parallel is read between successive programming pulses to determine whether it is equal to or greater than a verify level to which the element is being programmed.
For some architectures, thousands of memory cells can be programmed, read, or erased at the same time. For example, with a NAND architecture the control gates of thousands of memory cells may be connected together into what is commonly referred to as a word line. Thus, by applying a program voltage to the word line, thousands of memory cells can be programmed at a time. Likewise, by applying a read voltage to the word line, thousands of memory cells can be read at a time. Similarly, by applying an erase voltage to a common well region for the memory cells a block of many memory cells may be erased.
A memory array may have many bit lines, each used as a control line for a different set of memory cells. During programming, a program enable or a program inhibit voltage may be applied to a bit line to facilitate or inhibit programming of a memory cell coupled to the bit line and a selected word line. For reading, a pre-charge voltage may be applied to the selected bit lines. During erasing, the bit line switch transistors may be turned off to isolate the bit lines.
One technique for applying the necessary voltages to the bit lines is through a bit line switch transistor that is connected to each bit line. Large voltages may be associated with the bit line switch transistors. For example, a high erase voltage may couple to the bit line terminal of a BL switch transistor during erasing or a high select voltage may be applied to the gates of the BL switch transistors during programming or reading. The operation of the bit line switch transistors at the necessary levels may cause problems with the transistors in traditional architectures.